1. Field of the Invention
The present invention is related to electronic and computer system communications, and more particularly to an apparatus and method for high speed digital communication.
2. Background Information
In the electronic circuit and computer industries the current trend is toward designing and building systems which operate at ever increasing clock speeds. In addition, there is wide-spread use of multiple integrated circuits in these systems, all of which are interconnected to achieve greater processing power and promote efficiency. As clock speeds continue to increase, the time to transfer data between interconnected integrated circuits has surpassed a single clock period.
An interconnect path greater than a single clock period is called a multiple-clock path. It is called a multiple-clock path because the communication route between one circuit and another is long enough that it takes multiple-clock periods for transmitted information to arrive at a receive circuit. These multiple-clock paths introduce a number of difficulties into system design, all related to handling the transmitted data at a receiving circuit.
A first method used to allow multiple-clock paths in a system is a synchronous design where the multiple integrated circuits operate from the same clock. While this type of solution allows for multiple-clock period paths it introduces difficult short-path issues that violate hold times for the receiving circuits. These problems require minimum distances between integrated circuits, extra padding in the interconnects, or additional integrated circuit logic.
Another attempted solution for the multiple-clock path problem is a complex source-synchronous channel protocol. Here, a complex forwarded clock scheme is used where the timing between the forwarded clock and the receiving chip clock is not known. This solution requires a data verification and resynchronization sequence at the receiving circuit. This complex source-synchronous channel protocol significantly increases latency in the channel while adding significant levels of design complexity in the receiving circuit.
Thus, there is a need for a method and apparatus for high speed digital communication that allows for high-bandwidth, low-latency communication where the transmit time between circuits is greater than a single period of the system clock. Additionally, the system needs to guarantee data integrity by meeting the minimum and maximum timing constraints of the receive circuits without adding excess design complexity.
The present invention provides a system and method for efficient high speed, high bandwidth, digital communication where transmit distances are greater than a single clock period. The system and method operate utilizing a synchronized design that takes advantage of a forwarded clock and pairs of memory devices to quickly latch data into a receiving circuit without violating timing constraints. A multiplexor is then used to allow the data to be available almost immediately for processing in the receiving circuit without any corruption of data, even when operating at very high speeds. Additionally, the system, since it uses a minimum amount of circuitry, avoids complexity while reducing the latency of transmitted data.
According to one aspect of the present invention, a digital system operates based on a system clock. Within the digital system a transmit module transmits data along with a capture clock signal to a receive module where the transmission time between the modules is greater than one period of the system clock. The capture clock operates in a known relationship to the system clock at a frequency at least twice as slow as the system clock. The digital system also has a synchronizing clock that operates at the same frequency as the forwarded clock. When the data arrives at the receive module it is captured by a pair of memory devices operating on different phases of the capture clock. The memory devices feed the data to a multiplexor that selects, as a function of the synchronizing clock, between the outputs of the two memory devices. At this point the data has been synchronized with the system clock and can be captured using the system clock for processing in the receive module.
According to another aspect of the present invention, an integrated circuit is operated using a system clock. The integrated circuit also has a capture clock that operates in a known relationship to the system clock at a frequency at least twice as slow as the system clock and a synchronizing clock that operates at the same frequency as the capture clock. Within the integrated circuit there is a transmit subcircuit that has a transmit memory device and an output for the capture clock. Connected to the transmit subcircuit is a receive subcircuit. The receive subcircuit has a first memory device connected to the transit memory device and operates on a first phase of the capture clock. The receive subcircuit also has a second memory device connected to the transmit memory device and operates on a second phase of the capture clock. The receive subcircuit then has a multiplexor having one input connected to the output of the first memory device and a second input connected to the output of the second memory device and an output select node that is connected to the synchronizing clock. The output of the multiplexor is connected to an input memory device that is operated on the system clock.
Yet another aspect of the present invention is a system operated at a first clock frequency that has a receive module having a pair of memory devices. The system generates both a forwarded clock that operates at a frequency at least twice as slow as the first clock and a receive clock that operates at the same frequency as the forwarded clock. The system then transmits data and the forwarded clock from a transmit module to the receive module. The receive module stores the transmitted data into a pair of memory devices, each memory device operating on a different phase of the forwarded clock. The data out of the pair of memory devices is first synchronized with the receive module using the receive clock and then captured for further processing using the first clock.